LEON2FT processor

LEON2FT processor

Released

01/01/1970 1:33 am

Copyright

ESA

Description

Layout of the fault-tolerant LEON2FT processor, implemented by the section in UMC 0.18 µm technology. Engineers made this test chip to investigate the radiation tolerance of commercial ASIC technologies with an SEU hardened design; it has also provided valuable design experience with the LEON VHDL model, which benefits other ESA developments.

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